The present invention is concerned with a device for receiving width modulated digital data pulses and more particularly with detection and correction of signal transitions for data pulses received from a noisy or lengthy capacitive line, or combination of both.
While there are many encoding techniques employed to change an incoming serial binary data stream into a frequency modulated digital signal, frequently this is done by changing binary data into a stream of variable width data pulses where any pulse width is a multiple of a basic value. A pulse is therefore delimited by the change of value only and not by the data value itself. Thus, for any given pulse, data can have either 1 or 0 logical values.
When sending such encoded signal pulses over long transmission lines it is important that "n", the value of the multiple of the basic or minimum value TWm for a pulse width (TWi) be as small as possible. However, it cannot be smaller than 2, since two binary values have to be encoded. Furthermore the correct reception of the encoded signal is not possible without unique synchronization markers. Therefore in most cases "n" has a value not less than 3.
The transmission of encoded data is typically preceded by a synchronization sequence during which a number of constant width data pulses, (usually with TW =TWm) and a unique synchronization marker allow the receiver to currently identify the beginning of the data sequence. Improving signal t o noise ratio at the receiver end of the transmission line has often been achieved through the use of low pass filters that reject high frequency noise that most affects signal reception. To a degree, however, these filters also distort the useful digital signal. On the other hand, long transmission lines that exhibit a capacitive impedance act themselves as low pass filters for the digital signal they carry. The resulting signal waveform at the receiver end is characterized by low amplitude and slow rise and fall times that can be reliable translated to logic levels only by line receivers with hysteresis characteristics. The line and filter capacitive loads, filtered noise, and circuit nonlinearity among other factors, cause an unwanted side effect whereby there is a time difference between expected and actual values of signal pulse widths, commonly known as jitter.
Prior art decoding devices have concentrated on determining the proper width value by measuring TW actual and adjusting it to the closest expected value, TWexpected. The bigger the jitter, the more difficult it is to decode the received digital signal. In general the absolute jitter value has to be less than 0.5 TWi for the received signal to be properly decoded.
It is therefore the object of this invention to provide a method and a device that are capable of predicting positions for signal transitions when expected pulse widths are a multiple of a basic value.
Another object of this invention is the provide a device that, when connected to an incoming signal consisting of digital data pulses is capable of detecting and correcting shifted signal transitions such that the resulting signal can be decoded error free.
A further object of this invention is to provide a device that when connected to a signal of the type described above is capable of correcting pulse width that in certain cases exhibit jitter greater than one half t he width of the pulse.
A still further object of this invention is provide a device which maintains synchronism with a data transmitter even when the transmitter and receiver clocks are out of synchronism.
Another object of this invention is to provide a relatively simply and inexpensive device of the type described above.